1. Field of the Invention
The present invention relates to a novel digital accumulate and scale circuit. More particularly, the present invention relates to a novel input accumulator in the novel accumulate and scale circuit which is only as wide as the input data stream and the additional most significant bits for the novel accumulator are generated at the output of the accumulator by an up/down counter coupled to the output carry of the input accumulator.
2. Description of the Prior Art
Heretofore, analog accumulate and scale circuits were known. An analog example of such circuit is an integrate and dump circuit which is not easily programmed. Further, digital equivalents of the analog continuous integrate and dump circuits are known. The digital accumulators of such digital accumulate and dump circuits require as many adder stages as are desired to accommodate the maximum range of binary numbers in the output of the accumulator. When a large output stage is to be provided in a digital accumulator, it requires a large amount of adder time to propagate the carries to the highest order stages. One method of reducing this propagation time is to employ a pipeline adder or adders. The penalty for decreasing propagation time using such pipeline adders is that more complex circuitry is required which is more difficult to implement in hardware and also requires more chip real estate when implemented in very large scale integrated circuit form.
It would be highly desirable to provide a programmable digital integrate and scale circuit which embodies all of the advantages of pipeline adders without the penalties of the complex and more expensive circuitry.